The Accelerator Coherency Port (ACP) on the Zynq PS is an AXI3-compatible 64-bit slave interface that connects to the SCU (Snoop Control Unit), providing the PL with asynchronous cache coherency to directly access the PS entry.
The processor can mark the transmission on the ACP as consistent or non-uniform. The AXI host on the PL side indicates whether it is a consistent read transfer through ARUSERS[1:0], and the write transfer is indicated by AWUSERS[1:0]. These signals are all AXI bus related signals. Devices or strong requests for sequential transmission are often treated as non-conforming transmissions (these are transmissions generated by the AXI host interface, they are not cached, often resulting in fixed size and number of transmissions).
[Introduction]
The non-conforming transmission goes directly through the SCU and appears on the AXI host interface.
The ACP slave's consistent transfer to the AXI host will become more or less transmitted, and some properties will change.
When the ACP receives a consistent write request from an external host, the SCU checks the corresponding address in the CPU core L1 data cache. If it hits, the coherency protocol clears and invalidates the corresponding cache line, and merges the cleared data and write request.
When a read request is initiated from the external host box coherent memory area, it interacts with the SCU to test whether data needs to be stored in the processor L1 Cache. If it hits, the SCU directly returns data to the requester; if miss, the SCU checks the L2 cache first, and then Otherwise access to main memory.
[ACP request]
ACP Consistent Read Request: When ARUSER[0] == 1, ARCACHE[1] ==1, and ARVALID is valid, an ACP Consistent Read Request is generated. At this point, the SCU enforces consistency.
When ARUSER[0] == 0 or ARCACHE[1] ==0, and the ARVALID is valid, an ACP non-conformance read request is generated. At this time, the SCU does not enforce consistency, and the read request is passed directly to the available SCU AXI master port to the L2 Cache controller or OCM.
ACP Consistent Write Request: When AWUSER[0] == 1 and AWCACHE[1] == 1, and AWVALID is valid, an ACP Consistent Write Request is generated. At this time, the SCU enforces consistency. When the data exists in a Cortex-A9 processor, the PS area logic first clears and invalidates the data of the corresponding CPU. When the data is not in any CPU, or when it has been cleared, invalidate, the write request is initiated to the L2 Cache or main memory through the AXI host interface of a Cortex-A9 processor.
When AWUSER[0] ==0 or AWCACHE[1] ==0, and AWVALID is valid, an ACP non-conforming write request is generated. At this point the SCU does not enforce consistency and the write request is passed directly to an available SCU AXI master port.
[ACP restrictions]
Consistent access does not allow exclusive access;
Consistent access does not allow locked access;
Write transfer, length = 3, size = 3, write strobe 11111111 will cause CPU cache line damage;
Continuous access to OCM via ACP may starve other AXI hosts; limit burst size to less than 8 x 64bit words.
ã€references】
Zynq-7000 EPP TRM (UG585)
The Effect and Technique of System Coherence in ARM MulTIcore Technology by John Goodacre, Senior Program Manager, ARM Processor Division
ARM Cortex-A9 MPCore TRM, secTIon 2.4, Accelerator Coherency Port
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