In a 32-bit ARM system, a branch instruction or a PC register load instruction is generally placed in the interrupt vector table to implement the function of the program jump to the interrupt service routine. E.g:
IRQEntry B HandleIRQ ; smaller jump range
B HandleFIQ
Or IRQEntry LDR PC, =HandleIRQ ; the range of the jump is any 32-bit address space
LDR PC, =HandleFIQ
The LDR pseudo-instruction equivalently generates one memory read instruction and one 32-bit constant definition instruction. The 32-bit constant is stored in a location near the LDR instruction with a relative offset of less than 4KB. The 32-bit data is the interrupt service program entry address to jump to.
The reason why the LDR pseudo instruction is used is because the ARM RISC instruction is a single word instruction and cannot load a 32-bit immediate value (constant). It is not possible to directly load a 32-bit constant data or address data into a register. The following general procedure is equivalent to the above pseudo-instruction function, but the interrupt vector table is described more clearly. Where VectorTable is the offset from the LDR instruction:
IRQEntry LDR PC, VectorTable+0
; equivalent to LDR PC, =HandleIRQ
LDR PC, VectorTable+4
; equivalent to LDR PC, =HandleFIQ
......
VectorTable DCD HandleTRQ
DCD HandleFIQ
......
HandleIRQ
......
HandleFIQ
Generally, the programs of the ARM embedded system are solidified in the low-end ROM space starting from 00000000H, and the interrupt vector table VectorTable is also solidified in the ROM, so neither of the above methods can dynamically modify the interrupt vector table dynamically during program running. Regardless of the programmer who is a beginner ARM processor or an experienced programmer, setting the interrupt vector is quite cumbersome. You must modify the startup code of the ARM C program. A lengthy assembly code is inconvenient and error-prone.
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