Learning FPGA is actually not too long. At the beginning, I didn't refer to other people's codes much. Most of them were written by myself. At that time, I did more sequential logic. Participating in the embedded training course, I have worked hard for more than a month to be familiar with the use of ISE software and verilog grammar, and I have also consulted many books, which is considered to have laid a good foundation for myself. Because the direction of training was software radio at that time, I made a lot of related module programs, and published a lot in the previous log. The key is an interest. I feel that after the simulation, I see that my algorithm ideas are realized. sense. Later, I stopped for a while, because there was really no more interesting work to do.
Until some time ago, I started to use the SP306 development board, and then I would refer to their code and benefit a lot. Now the team leader has done the work, and I am familiar with all the big projects. Then the code of the FPGA that is the master control has started to go on the master attack, and the code of the predecessors must be digested, and then updated. Good service for the next-generation upgraded version of the product. This verilog program is estimated to be a headache for everyone. Small modules are no problem, and large modules and large projects are sometimes more difficult to start, because the design of HDL is different from software programming, and software is actually nothing more than a big while. Or there will be some interruptions, most of which are executed sequentially, and you will always figure it out if you slowly go down step by step. HDL has a strong parallelism. If you follow the software's thinking, it will definitely not work, so what should I do? I'll just talk about some quick-advanced tips of my own.
Since the HDL design is parallel, it can only be broken individually. My habit is to first grab a few important ports, such as clock (CLK), reset (RESET) and other ports with a higher frequency, and figure it out first, such as what frequency is the clock? Is reset active high or low?
Then, it is best to understand the program against the schematic diagram. This requires you to have a certain degree of hardware knowledge. You must know the timing of the operation of some commonly used devices, at least you must know one or two, so that you can achieve a multiplier effect when you read the program. According to the ratio, you must first understand the program of FPGA and AD chip, then you first analyze the places where the AD ports (such as chip select, read/write, conversion, conversion completion interrupt, etc.) appear in the verilog program. For example, if I look for the CS signal to see when it is active low, then you can enter CS in the Find in file window, and then ENTER, so that ISE will list all the statements that use the CS signal in the bottom information window. To facilitate your search and analysis, you have analyzed every place where CS appears, then you will understand how Verilog operates CS signals on the hardware. After all the signals are analyzed, I think you will understand the interface between AD and FPGA.
Reading Verilog is sometimes tiring, because the program is written by others, and it is inevitable that you have to let others lead by the nose. The key is to have patience, more analysis, and if possible, you can ask a master (preferably the author of the code).
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